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教師資料查詢 | 教師：鄭國興

# 學年期 類別 標題
1 110-2 教學計畫表 電機系電資二：電子學 TETDB2E0961 2A
2 110-1 教學研習 MS Teams操作與iClass 學習平台導入工作坊（2021-09-15 09:00:00 ~ 12:00:00）
3 110-1 教學計畫表 電機系電資二：電子學 TETDB2E0961 1A
4 90-1 會議論文 A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning
5 90-1 會議論文 A 1.2 V 500 MHz 32-bit carry-lookahead adder
6 90-1 會議論文 Accurate current mirror with high output impedance
7 90-1 會議論文 A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
8 89-2 會議論文 A low-power high driving ability voltage control oscillator used in PLL
9 89-2 會議論文 A new logic synthesis and optimization procedure
10 88-1 會議論文 The non-full voltage swing TSPC (NSTSPC) logic design
11 88-1 會議論文 The novel efficient design of XOR/XNOR function for adder applications
12 88-2 會議論文 The Design and implementation of DCT/IDCT Chip with Novel Architecture
13 84-2 會議論文 True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
14 83-2 會議論文 A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
15 85-2 會議論文 A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
16 84-2 會議論文 A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications
17 87-1 會議論文 The Improvement of Conditional Sum Adder for Low Power Applications
18 87-2 期刊論文 The charge-transfer feedback-controlled split-path CMOS buffer
19 88-1 會議論文 A Low-Power CMOS Output Buffer
20 92-1 會議論文 Design of Low-Power Content Addressable Memory Cell
21 92-1 會議論文 A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
22 86-1 會議論文 A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
23 86-1 會議論文 The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer
24 86-1 會議論文 A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
25 84-1 會議論文 Rule Extraction for Isolated Speech Recognition
26 91-1 會議論文 Low-Voltage GHz Dynamic Logic Circuit Design
27 91-1 會議論文 MOS Charge Pump for Sub-2.0V Operation
28 80-2 會議論文 High-speed four-phase CMOS logic for complex high-speed VLSI
29 78-1 會議論文 Latched CMOS differential logic(LCDL)for complex high-speed VLSI
30 80-1 期刊論文 Latched CMOS differential logic(LCDL)for complex high-speed VLSI