A low-jitter and low-power phase-locked loop design
學年 88
學期 1
發表日期 2000-05-28
作品名稱 A low-jitter and low-power phase-locked loop design
作品名稱（其他語言）
著者 鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen; Tzou, Lin-jiunn
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
會議地點 Geneva, Switzerland
摘要 This paper describes a design of digital phase-locked loop (DPLL), which has low-power consumption and low jitter features. A novel voltage controlled oscillator (VCO) and Phase-Frequency Detector (PFD) are proposed to reduce the total power consumption and phase error of the DPLL. The proposed VCO has low power consumption, and the PFD is a “three-state” structure with a dead zone of 5 ps. The power consumption of the proposed DPLL is lower than 6.7 mW, and the output-frequency range of the oscillator is from 200 MHz to 650 MHz. The worst-case cycle jitter is lower than 160 ps, and long-term jitter is lower than 220 ps. We confirm the results based on 0.5 μm CMOS technology and 3 V supply voltage.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20000528~20000531
通訊作者
國別 CHE
公開徵稿
出版型式 紙本
出處 Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.257-260
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