教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:Latched CMOS differential logic(LCDL)for complex high-speed VLSI
學年
學期
發表日期1989/09/01
作品名稱Latched CMOS differential logic(LCDL)for complex high-speed VLSI
作品名稱(其他語言)
著者Wu, Chung-yu; Cheng, Kuo-hsing
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱Proceedings of 3rd international symposium on IC design and manufacture
會議地點Singapore
摘要A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間
通訊作者
國別新加坡
公開徵稿Y
出版型式紙本
出處Proceedings of 3rd international symposium on IC design and manufacture, pp.1324 - 1328
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