教師資料查詢 | 類別: 期刊論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:Analysis and design of a new race-free four-phase CMOS logic
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出版(發表)日期1993/01/01
作品名稱Analysis and design of a new race-free four-phase CMOS logic
作品名稱(其他語言)
著者Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan
單位淡江大學電機工程學系
出版者Piscataway: Institute of Electrical and Electronics Engineers (IEEE)
著錄名稱、卷期、頁數IEEE Journal of Solid-State Circuits 28(1), pp.18-25
摘要In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structured as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design.
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語言英文
ISSN0018-9200
期刊性質國外
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