教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:High efficient 3-input XOR for low-voltage low-power high-speed applications
學年
學期
發表日期1999/08/23
作品名稱High efficient 3-input XOR for low-voltage low-power high-speed applications
作品名稱(其他語言)
著者Cheng, Kuo-hsing; Hsieh, Ven-chieh
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
會議地點Seoul, Korea
摘要A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間19990823~19990825
通訊作者
國別韓國
公開徵稿Y
出版型式紙本
出處ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on, pp.166-169
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