High efficient 3-input XOR for low-voltage low-power high-speed applications
學年 87
學期 1
發表日期 1999-08-23
作品名稱 High efficient 3-input XOR for low-voltage low-power high-speed applications
作品名稱（其他語言）
著者 Cheng, Kuo-hsing; Hsieh, Ven-chieh
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
會議地點 Seoul, Korea
摘要 A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 19990823~19990825
通訊作者
國別 KOR
公開徵稿 Y
出版型式 紙本
出處 ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on, pp.166-169
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