| 標題：The charge-transfer feedback-controlled split-path CMOS buffer |
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| 學年 | 87 |
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| 學期 | 2 |
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| 出版（發表）日期 | 1999/03/01 |
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| 作品名稱 | The charge-transfer feedback-controlled split-path CMOS buffer |
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| 作品名稱（其他語言） | |
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| 著者 | Cheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi |
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| 單位 | 淡江大學電機工程學系 |
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| 出版者 | New York: Institute of Electrical and Electronics Engineers (IEEE) |
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| 著錄名稱、卷期、頁數 | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46(3), pp.346-348 |
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| 摘要 | Abstract—A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the shortcircuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper buffer at 100 MHz operation frequency. |
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| 關鍵字 | |
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| 語言 | 英文 |
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| ISSN | 1057-7130 |
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| 期刊性質 | 國外 |
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| 收錄於 | SCI;EI |
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| 國別 | 美國 |
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