教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:High-speed four-phase CMOS logic for complex high-speed VLSI
學年
學期
發表日期1992/05/10
作品名稱High-speed four-phase CMOS logic for complex high-speed VLSI
作品名稱(其他語言)
著者Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱Proceedings of 1992 IEEE international symposium on circuits and systems
會議地點San Diego, CA
摘要A novel four-phase dynamic logic, called high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than that of the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution
關鍵字
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19920510~19920513
通訊作者
國別美國
公開徵稿Y
出版型式紙本
出處Proceedings of 1992 IEEE international symposium on circuits and systems, pp.1288 - 1291
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