Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
學年 82
學期 2
發表日期 1994-05-30
作品名稱 Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
作品名稱（其他語言）
著者 Tseng, Yuh-kuang; 鄭國興; Cheng, Kuo-hsing; Wu, Chung-yu
作品所屬單位 淡江大學電機工程學系
出版者 Institute of Electrical and Electronics Engineers (IEEE)
會議名稱 Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
會議地點 London, England, UK
摘要 This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed. Structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage.
關鍵字
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 19940530~19940602
通訊作者
國別 GBR
公開徵稿
出版型式
出處 Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, vol.4, pp.23-26
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