關鍵字:

教師資料查詢 | 教師:鄭國興

# 學年期 類別 標題
6 87-1 期刊論文 Design and analysis of low-voltage current mode operational amplifier with differential-input and differential-output
7 90-1 會議論文 A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning
8 90-1 會議論文 A 1.2 V 500 MHz 32-bit carry-lookahead adder
9 90-1 會議論文 Accurate current mirror with high output impedance
10 90-1 會議論文 A difference detector PFD for low jitter PLL
11 90-1 會議論文 A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
12 89-2 會議論文 A low-power high driving ability voltage control oscillator used in PLL
13 89-2 會議論文 A new logic synthesis and optimization procedure
14 88-1 會議論文 The non-full voltage swing TSPC (NSTSPC) logic design
15 87-1 會議論文 High efficient 3-input XOR for low-voltage low-power high-speed applications
16 88-1 會議論文 The suggestion for CFS CMOS buffer
17 88-1 會議論文 The novel efficient design of XOR/XNOR function for adder applications
18 88-2 會議論文 The Design and implementation of DCT/IDCT Chip with Novel Architecture
19 88-1 會議論文 A low-jitter and low-power phase-locked loop design
20 84-2 會議論文 True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
21 83-2 會議論文 A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
22 85-2 會議論文 A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
23 85-2 會議論文 Design of current mode operational amplifier with differential-input and differential-output
24 84-2 會議論文 A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications
25 82-2 會議論文 Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
26 87-1 會議論文 The Improvement of Conditional Sum Adder for Low Power Applications
27 87-2 期刊論文 The charge-transfer feedback-controlled split-path CMOS buffer
28 81-1 期刊論文 Analysis and design of a new race-free four-phase CMOS logic
29 78-1 會議論文 Latched CMOS differential logic(LCDL)for complex high-speed VLSI
1 80-1 期刊論文 Latched CMOS differential logic(LCDL)for complex high-speed VLSI
2 110-2 教學計畫表 電機系電資二:電子學 TETDB2E0961 2A
3 110-1 教學研習 MS Teams操作與iClass 學習平台導入工作坊(2021-09-15 09:00:00 ~ 12:00:00)
4 110-1 教學計畫表 電機系電資二:電子學 TETDB2E0961 1A
5 100-1 期刊論文 Latched CMOS differential logic(ALCDL)and its application in the design of high-speed parallel multipliers
30 80-2 會議論文 High-speed four-phase CMOS logic for complex high-speed VLSI