期刊論文

學年期 標題 更新時間
097 / 2 Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique 2017/01/04
098 / 1 Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications 2017/01/13
099 / 1 High Efficiency Concurrent Embedded Block Coding Architecture for JPEG 2000 2017/01/13
099 / 1 A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process 2013/10/30
091 / 2 Circuit analysis and design of low-power CMOS tapered buffer 2013/12/31
092 / 1 A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop 2014/03/28
093 / 1 低功率多輸出入埠暫存器檔案之分析與設計 2012/07/02
093 / 1 動態調整電源電壓與操作頻率以降低系統晶片之功率消耗 2012/07/02
097 / 2 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer 2013/11/08
098 / 2 A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output 2013/11/08
099 / 1 The High-Performance and Low-Power CMOS Output Driver Design 2013/11/08
101 / 1 Low-Power Fast-Settling Low-Dropout Regulator Using a Digitally Assisted Voltage Accelerator for DVFS Application 2017/02/15
101 / 2 A new phase interpolator circuit for frequency multiplication design in embedded system 2016/12/05
102 / 1 A multiple frequency clock generator using wide operation frequency range phase interpolator 2017/12/18
100 / 1 A synthesizable pseudo fractional-N clock generator with improved duty cycle output 2014/03/07
103 / 2 A Robust Oscillator for Embedded System without External Crystal 2018/09/04
087 / 2 The charge-transfer feedback-controlled split-path CMOS buffer 2015/06/16
104 / 2 A 25 MHz crystal less clock generator with background calibration against process and temperature variation 2017/10/24
104 / 2 A High-Resolution All-Digital Temperature Sensor with Process Variation Compensation 2016/11/22
104 / 2 A High-Resolution All-Digital Temperature Sensor with Process Variation Compensation 2019/08/20
106 / 1 Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage 2018/09/04
106 / 1 A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4 2019/08/20
105 / 1 All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application 2019/08/28
106 / 1 A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator 2019/08/28
106 / 1 Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input 2019/08/28
107 / 2 A Fast Transient Response and High Current Efficiency Output-Capacitorless Low Dropout Regulator for Low-Power SoC Applications 2020/07/14
108 / 2 A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications 2020/07/16