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標題
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A synthesizable pseudo fractional-N clock generator with improved duty cycle output |
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學年
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100 |
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學期
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1 |
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出版（發表）日期
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2011/10/01 |
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作品名稱
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A synthesizable pseudo fractional-N clock generator with improved duty cycle output |
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作品名稱（其他語言）
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著者
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Yang, Wei-Bin; Hsieh, Chang-Yo |
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單位
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淡江大學電機工程學系 |
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出版者
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London: Elsevier Ltd |
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著錄名稱、卷期、頁數
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Microelectronics Journal 42(10), pp.1099-1106 |
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摘要
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A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz. |
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關鍵字
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Synthesizable; Clock generator; Pseudo fractional-N; Duty cycle |
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語言
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英文(美國) |
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ISSN
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0026-2692 |
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期刊性質
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國外 |
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收錄於
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SCI |
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產學合作
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通訊作者
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Ynag, Wei-Bin |
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審稿制度
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國別
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英國 |
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公開徵稿
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出版型式
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紙本 |