期刊論文
| 學年 | 108 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 2020-03-06 |
| 作品名稱 | A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications |
| 作品名稱（其他語言） | |
| 著者 | Wei-Bin Yang; Hsi-Hua Wang; Hsin-I Chang; Yu-Lung Lo |
| 單位 | |
| 出版者 | |
| 著錄名稱、卷期、頁數 | Japanese Journal of Applied Physics 59(SG), SGGL08 |
| 摘要 | This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μs which is 35 TREF, and core area was 0.291 mm2. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 1347-4065;0021-4922 |
| 期刊性質 | 國外 |
| 收錄於 | SCI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | GBR |
| 公開徵稿 | |
| 出版型式 | ,電子版,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/118937 ) |