期刊論文
| 學年 | 97 |
|---|---|
| 學期 | 2 |
| 出版（發表）日期 | 2009-06-01 |
| 作品名稱 | High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer |
| 作品名稱（其他語言） | |
| 著者 | Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Tokyo: Denshi Jouhou Tsuushin Gakkai |
| 著錄名稱、卷期、頁數 | IEICE Transactions on Electronics E92-C(6), pp.890-893 |
| 摘要 | A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35μW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang’s counter [1], and the E-TSPC counter [2], respectively. |
| 關鍵字 | dynamic D flip-flops; counters; prescalers; ultra-low-voltage design |
| 語言 | en |
| ISSN | 0916-8524; 1745-1353 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | Lo, Yu-lung |
| 審稿制度 | |
| 國別 | JPN |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60960 ) |