期刊論文

標題 Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input
學年 106
學期 1
出版(發表)日期 2017/12/01
作品名稱 Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input
作品名稱(其他語言)
著者 Wei‑Bin Yang; Yu-Yao Lin; Yu-Lung Lo
單位
出版者
著錄名稱、卷期、頁數 Circuits, Systems, and Signal Processing 36(12), p.5041-5061
摘要 This paper proposes a new design for a fast-locked digitally controlled low-dropout regulator (FDLDO) for an ultra-low voltage input. The proposed design involves a fast-locked control mechanism that reduces the settling time of the load transient response in the tracking mode and decreases the quiescent current in the regulating mode. For an ultra-low input voltage of 0.35 V, the proposed FDLDO is capable of providing a regulated output voltage of 0.3 V with a dropout voltage of 50 mV and delivering a maximal load current of 2.4 mA with current and power efficiencies of 99.74 and 85.49%, respectively. Measurement results showed that in the regulating mode, the quiescent current is only 5.15 μAμA for the maximal load current; furthermore, for the maximal load current, the load regulation and the line regulation are 1.5 mV/mA and 4.916 mV/V, respectively. Under the load regulation, the transient response time is less than 15 μsμs. No external output capacitor is required to stabilize the control loop, and there is no external input clock. The proposed FDLDO is suitable for low-power system-on-a-chip applications of wearable electronic devices with an ultra-low supply voltage.
關鍵字 Fast-locked digitally controlled low-dropout regulator (FDLDO); Ultra-low voltage; Fast-locked control mechanism; Load regulation; Line regulation; Wearable electronic devices
語言 英文(美國)
ISSN
期刊性質 國外
收錄於 SCI;EI;
產學合作
通訊作者
審稿制度
國別 德國
公開徵稿
出版型式 ,電子版