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標題
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A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output |
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學年
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98 |
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學期
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2 |
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出版（發表）日期
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2010/03/01 |
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作品名稱
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A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output |
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作品名稱（其他語言）
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著者
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Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng |
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單位
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淡江大學電機工程學系 |
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出版者
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Tokyo: Denshi Jouhou Tsuushin Gakkai |
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著錄名稱、卷期、頁數
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IEICE Transactions on Electronics E93-C(3), pp.309-316 |
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摘要
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A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 μm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 μW at 304 MHz. |
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關鍵字
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fractional-N; clock generator; pseudo fractional-N controller; duty cycle |
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語言
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英文 |
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ISSN
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0916-8524; 1745-1353 |
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期刊性質
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國外 |
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收錄於
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SCI;EI |
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產學合作
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通訊作者
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Yang, Wei-Bin |
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審稿制度
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是 |
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國別
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日本 |
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公開徵稿
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出版型式
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紙本 |