標題
|
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique |
學年
|
97 |
學期
|
2 |
出版(發表)日期
|
2009/05/01 |
作品名稱
|
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique |
作品名稱(其他語言)
|
|
著者
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
單位
|
淡江大學電機工程學系 |
出版者
|
Piscataway: Institute of Electrical and Electronics Engineers |
著錄名稱、卷期、頁數
|
IEEE Transactions on Circuits and Systems II: Express Briefs 56(5), pp.339-343 |
摘要
|
This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13-mum standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 mm2. |
關鍵字
|
|
語言
|
英文 |
ISSN
|
1549-7747 |
期刊性質
|
國外 |
收錄於
|
SCI;EI; |
產學合作
|
|
通訊作者
|
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
審稿制度
|
否 |
國別
|
美國 |
公開徵稿
|
|
出版型式
|
,電子版,紙本 |