期刊論文

標題 A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator
學年 106
學期 1
出版(發表)日期 2017/11/01
作品名稱 A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator
作品名稱(其他語言)
著者 Wei‑Bin Yang; Ming-Hao Hong; Jsung Mo Shen
單位
出版者
著錄名稱、卷期、頁數 Journal of Signal Processing Systems 89(2), p.347-362
摘要 This paper presents a selectable discrete-voltage output and fast-settling low-dropout regulator (LDO) by using half digitally-assistant voltage accelerator. The transition response time within reference switching and transient load regulation is significantly reduced by utilizing the discrete-voltage control technique and the half digitally-assistant voltage accelerator. The proposed LDO regulator provides two selectable discrete-voltage outputs of 2.8 V and 1.8 V by using the discrete-voltage control technique. The settling time is reduced by utilizing the half digitally-assistant voltage accelerator when the output voltage is switching. Furthermore, the new comparator architecture is proposed to avoid large under−/over-shoot voltage of the LDO output. According to the experimental results, the settling time of the proposed LDO regulator can be significantly reduced from 4.2 ms to 14.892 μs. Moreover, the discrete-voltage control unit and the half digitally-assistant voltage accelerator of the proposed LDO regulator consume only 0.11 mW under a load current of 100 mA. The figure of merit (FOM) of the proposed LDO regulator is improved by over 20 %, in comparison to previous works.
關鍵字 Low-dropout regulator; Discrete-voltage control unit; Half digitally-assistant voltage accelerator; Fast-settling; New comparator architecture
語言 英文(美國)
ISSN
期刊性質 國外
收錄於 SCI;EI;
產學合作
通訊作者 [26] Wei‑Bin Yang
審稿制度
國別 德國
公開徵稿
出版型式 ,電子版,紙本