期刊論文
| 學年 | 105 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2017-01-30 |
| 作品名稱 | All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application |
| 作品名稱（其他語言） | |
| 著者 | Chih-Wei Tsai; Yu-Lung Lo; Chia-Chen Chang; Han-Ying Liu; Wei-Bin Yang; Kuo-Hsing Cheng |
| 單位 | |
| 出版者 | |
| 著錄名稱、卷期、頁數 | Japanese Journal of Applied Physics 56(4S), p.04CF02 |
| 摘要 | A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40–60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps. |
| 關鍵字 | |
| 語言 | en_US |
| ISSN | |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 否 |
| 國別 | JPN |
| 公開徵稿 | |
| 出版型式 | ,電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/112389 ) |