期刊論文

標題 A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
學年 99
學期 1
出版(發表)日期 2011/01/01
作品名稱 A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
作品名稱(其他語言)
著者 Yang, Wei-Bin; Liao, Chao-Cheng; Liang, Yung-Chih
單位 淡江大學電機工程學系
出版者 London: Elsevier Ltd
著錄名稱、卷期、頁數 Microelectronics Journal 42(1), pp.43–51
摘要 This paper presents an 8x8bit pipelined multiplier operating at 320MHz under 0.5V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5V. The proposed pipelined multiplier is fabricated in 130nm CMOS process. It operates up to 320MHz and the power consumption is only 1.48mW at 0.5V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5V is reduced over 5.7 times than that of the traditional architecture at 1.2V. Thus, the proposed 8x8bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.
關鍵字 Pipelined multiplier;Forward body bias;Modified full adder;New D flip-flop
語言 英文
ISSN 0026-2692
期刊性質 國外
收錄於 SCI;EI
產學合作
通訊作者 Yang, Wei-Bin
審稿制度
國別 英國
公開徵稿
出版型式 紙本