| 364 |
97-1
|
會議論文
|
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
|
| 365 |
94-1
|
會議論文
|
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle
|
| 366 |
101-1
|
會議論文
|
A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application
|
| 367 |
100-2
|
會議論文
|
A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS
|
| 368 |
100-1
|
會議論文
|
A New Temperature Independent Current Controlled Oscillator
|
| 369 |
100-1
|
會議論文
|
Temperature Insensitive Current Reference for the 6.27 MHz Oscillator
|
| 383 |
102-2
|
教學計畫表
|
電機系電資三:類比積體電路導論 TETAB3E2994 0A
|
| 384 |
102-2
|
教學計畫表
|
電機一博士班:超大型積體電路設計 TETXD1E1185 0A
|
| 385 |
102-2
|
教學計畫表
|
電機系電資四:特殊應用積體電路設計 TETAB4E2965 0A
|
| 370 |
100-1
|
會議論文
|
Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator
|
| 371 |
102-1
|
研究獎勵
|
A Synthesizable Pseudo Fractional-N Clock Generator with
Improved Duty Cycle Output
|
| 372 |
101-2
|
會議論文
|
A 1.8-V 4-ppm oC Reference Current with Process and Temperature
|
| 373 |
103-1
|
教學計畫表
|
電機系電資三:介面實驗 TETAB3E1563 0A
|
| 374 |
103-1
|
教學計畫表
|
電機系電資四:電子實驗 TETAB4E1568 0A
|
| 375 |
103-1
|
教學計畫表
|
電機一機器人:數位IC設計 TETEM1E2865 0A
|
| 376 |
103-1
|
教學計畫表
|
電機系電資三:電子學 TETAB3E0961 2A
|
| 377 |
103-1
|
教學計畫表
|
電機系電資三:超大型積體電路概論 TETAB3E0836 0A
|
| 378 |
102-2
|
會議論文
|
Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process
|
| 379 |
92-1
|
期刊論文
|
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
| 380 |
102-2
|
教學計畫表
|
電機系電資二:系專業客製化課程-電子學 TETAB2Z0019 1A
|
| 381 |
100-1
|
期刊論文
|
A synthesizable pseudo fractional-N clock generator with improved duty cycle output
|
| 382 |
102-2
|
教學計畫表
|
電機系電通一:基礎電機實驗 TETBB1E1562 2C
|
| 386 |
102-2
|
教學計畫表
|
電機系電資二:電子學 TETAB2E0961 1A
|
| 387 |
91-2
|
期刊論文
|
Circuit analysis and design of low-power CMOS tapered buffer
|
| 388 |
97-2
|
期刊論文
|
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
|
| 389 |
98-2
|
期刊論文
|
A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
|
| 390 |
99-1
|
期刊論文
|
The High-Performance and Low-Power CMOS Output Driver Design
|
| 361 |
98-1
|
會議論文
|
A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
|
| 362 |
92-2
|
會議論文
|
A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop
|
| 363 |
95-2
|
會議論文
|
A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
|