A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
學年 98
學期 1
發表日期 2009-12-14
作品名稱 A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
作品名稱（其他語言）
著者 Gao, Wan-lun; Yang, Wei-bin; Lo, Yu-lung
作品所屬單位 淡江大學電機工程學系
出版者 Nanyang Technological University; IEEE Singapore Section
會議名稱 2009 12th International Symposium on Integrated Circuits(ISIC '09)
會議地點 Singapore
摘要 Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in the same chip, in this paper, the new pseudo fractional-N and multiplier clock generator with low power phase combination controller and 50% duty cycle is proposed to achieve this purpose. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed fractional-N or multiplier clock frequencies with 50% duty cycle. Furthermore, the frequency of the output clock can be programmed by the low power phase combination controller. The circuits are processed in a standard 0.35μm CMOS technology, and work with a supply voltage of 3.3V. The simulation results demonstrate that the low power phase combination controller can save power dissipation from 9.7%~22.9%.
關鍵字 fractional; clock
語言 en_US
收錄於
會議性質 國際
校內研討會地點
研討會時間 20091214~20091216
通訊作者
國別 SGP
公開徵稿 Y
出版型式 紙本
出處 2009 12th International Symposium on Integrated Circuits(ISIC '09), pp.562 - 565
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