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標題:Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
學年
學期
發表日期2009/09/14
作品名稱Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
作品名稱(其他語言)
著者Chao, Ting-sheng; Lo, Yu-lung; Yang, Wei-bin; Cheng, Kuo-hsing
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱The 35th European Solid-State Circuits Conference (ESSCIRC '09)
會議地點Athens Greece
摘要This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.
關鍵字
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20090914~20090918
通訊作者
國別希臘
公開徵稿
出版型式紙本
出處The 35th European Solid-State Circuits Conference (ESSCIRC '09), pp.388 - 391
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