Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
學年 98
學期 1
發表日期 2009-09-14
作品名稱 Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
作品名稱（其他語言）
著者 Chao, Ting-sheng; Lo, Yu-lung; Yang, Wei-bin; Cheng, Kuo-hsing
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 The 35th European Solid-State Circuits Conference (ESSCIRC '09)
會議地點 Athens Greece
摘要 This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-μm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.
關鍵字
語言 en_US
收錄於
會議性質 國際
校內研討會地點
研討會時間 20090914~20090918
通訊作者
國別 GRC
公開徵稿
出版型式 紙本
出處 The 35th European Solid-State Circuits Conference (ESSCIRC '09), pp.388 - 391
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70374 )

機構典藏連結
SDGS 優質教育,可負擔的潔淨能源,產業創新與基礎設施