教師資料查詢 | 類別: 會議論文 | 教師: 楊維斌 Web-bin Yang (瀏覽個人網頁)

標題:A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
學年
學期
發表日期2006/12/12
作品名稱A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
作品名稱(其他語言)
著者Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱2006 The 13th IEEE International Conference onElectronics, Circuits and Systems (ICECS '06)
會議地點Nice, France
摘要A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high speed prescaler circuit. Prescaler and VCO are the main blocks that determining the speed of phase locked-loop (PLL). In this paper, a very low power-delay product divide-by 4/5 prescaler based on our DFIDFF is proposed. The prescaler implemented with 0.13 mum 1P8M N-well CMOS process with an ultra low 0.5 V power supply voltage. By HSPICE simulation results, the power-delay product (PDP) of the novel divided-by 4/5 prescaler can be reduced over 39% in comparison to conventional divided-by 4/5 prescaler. Moreover, the novel divided-by-4/5 prescaler circuit can operate at 613 MHz with the power consumption of 8.014 uW under a 0.5 V supply voltage.
關鍵字
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20061212~20061213
通訊作者
國別法國
公開徵稿Y
出版型式紙本
出處2006 The 13th IEEE International Conference onElectronics, Circuits and Systems (ICECS '06),pp.902 - 905
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