教師資料查詢 | 類別: 會議論文 | 教師: 楊維斌 Web-bin Yang (瀏覽個人網頁)

標題:Analysis and Design of High Performance, Low Power Multiple Ports
學年
學期
發表日期2006/12/04
作品名稱Analysis and Design of High Performance, Low Power Multiple Ports
作品名稱(其他語言)
著者Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu
作品所屬單位淡江大學電機工程學系
出版者IEEE
會議名稱2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006)
會議地點Singapore
摘要This paper talks about how to analyze and design high performance low power multiple-ports register file circuitry, which is mostly used on mu-P and DSP chip. Firstly, in this paper, we discuss basic concept of register files. Secondly we introduce the different types of register file architecture. Then we analyze and compare design trade-offs among those approaches. With that, we decide the suitable register file circuitry for our application. Then, we start to analyze the low power design style for each block. Finally, we achieve design goal of low power and high performance register file circuit compare to some other designs. It is fabricated by TSMC 0.13mum 1p8m 1.2v process. Simulation result shows the design has the fine 0.013 mW/MHz-port
關鍵字DSP;RISC processor;differential-End structure;register file;single-End structure
語言英文(美國)
收錄於
會議性質國際
校內研討會地點
研討會時間20061204~20061206
通訊作者
國別新加坡
公開徵稿
出版型式紙本
出處2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), pp.1453 - 1456
相關連結
SDGs
  • 優質教育,產業創新與基礎設施
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