A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
學年 96
學期 2
發表日期 2008-04-16
作品名稱 A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
作品名稱（其他語言）
著者 Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way
作品所屬單位 淡江大學電機工程學系
出版者 IEEE
會議名稱 2008 The 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008)
會議地點 Bratislava, Slovakia
摘要 In this paper, a 6GHz spread-spectrum clock generator (SSCG) for Serial AT Attachment Generations 3 (SATA-III) is presented. By utilizing frequency modulation which employs digital MASH delta-sigma modulator and 33KHz triangular profile address generator, the SSCG achieves an output clock of 6GHz and 5000ppm down spread with a triangular waveform. The SSCG was designed based on TSMC 0.13μm 1p8m CMOS process. The power dissipation is 48mW under a 1.2V supply voltage. The peak-to-peak jitter of non spread-spectrum clock is 8ps, and the EMI reduction is 15dB with normal frequency spread modulation from 6GHz to 5.97GHz.
關鍵字 CMOS integrated circuits;clocks;delta-sigma modulation;jitter;microwave generation;modulators
語言 en_US
收錄於
會議性質 國際
校內研討會地點
研討會時間 20080416~20080418
通訊作者
國別 SVK
公開徵稿 Y
出版型式 紙本
出處 2008 The 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2008),pp.1~4
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