會議論文

學年期 標題 更新時間
095 / 2 New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode 2014/09/09
094 / 2 The new improved pseudo fractional-N clock generator with 50% duty cycle 2014/09/09
098 / 1 Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique 2014/09/09
095 / 1 A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler 2014/09/09
101 / 2 A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved 2013/04/26
101 / 2 A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved 2014/09/22
098 / 1 A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller 2014/09/09
099 / 1 A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage 2012/03/19
100 / 1 Temperature Insensitive Current Reference for the 6.27 MHz Oscillator 2014/08/13
101 / 1 A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application 2014/08/22
101 / 2 A 1.8-V 4-ppm oC Reference Current with Process and Temperature 2014/07/02
102 / 1 A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration 2017/12/08
103 / 2 A Transient Enhanced LDO with Current Buffer for SoC Application 2017/12/11
104 / 2 A Current-Controlled Oscillator with Temperature, Voltage and Process 2017/12/11
094 / 1 The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle 2014/08/22
098 / 1 A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator 2014/09/09
097 / 1 A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage 2014/09/09
095 / 1 Analysis and Design of High Performance, Low Power Multiple Ports 2014/09/09
095 / 2 A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery 2014/09/09
098 / 1 A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator 2014/09/09
092 / 2 A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop 2014/09/09
099 / 2 The High-Performance and Low-Power CMOS Output Driver Design 2012/07/02
100 / 1 A New Temperature Independent Current Controlled Oscillator 2014/08/21
102 / 2 Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process 2014/05/20
103 / 2 A 25MHz Crystal Less Clock Generator with Background Calibration Against Process and Temperature Variation 2017/12/08
104 / 2 A fast-lock and low-power Delay-Locked-Loop applied for DDR4 2017/12/11
103 / 1 A new multiple frequency out of DLL with Glitch Elimination and Phase Interpolator 2017/12/11
105 / 2 A 12-bit 600MS/s CT ΣΔ ADC for Ultrasound System Applications 2017/12/11
106 / 2 The design of a crystal-off oscillator with robust on-chip PVT compensation 2018/10/22
106 / 2 Single-Inductor Dual-Output DC-DC Converters with new type ramp and clock generator 2018/10/22
096 / 2 A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III 2014/09/09
100 / 1 Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator 2014/08/13
100 / 2 A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS 2014/08/22
104 / 1 Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process 2016/05/16
102 / 2 Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process 2017/12/08
104 / 2 Wide Range CMOS Reference Clock Generator with Dynamic Duty Cycle Scaling Mechanism in 0.9V Supply Voltage 2017/12/11
103 / 1 A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO 2017/12/11