會議論文
| 學年 | 95 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2006-12-04 |
| 作品名稱 | Analysis and Design of High Performance, Low Power Multiple Ports |
| 作品名稱（其他語言） | |
| 著者 | Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | IEEE |
| 會議名稱 | 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006) |
| 會議地點 | Singapore |
| 摘要 | This paper talks about how to analyze and design high performance low power multiple-ports register file circuitry, which is mostly used on mu-P and DSP chip. Firstly, in this paper, we discuss basic concept of register files. Secondly we introduce the different types of register file architecture. Then we analyze and compare design trade-offs among those approaches. With that, we decide the suitable register file circuitry for our application. Then, we start to analyze the low power design style for each block. Finally, we achieve design goal of low power and high performance register file circuit compare to some other designs. It is fabricated by TSMC 0.13mum 1p8m 1.2v process. Simulation result shows the design has the fine 0.013 mW/MHz-port |
| 關鍵字 | DSP;RISC processor;differential-End structure;register file;single-End structure |
| 語言 | en_US |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20061204~20061206 |
| 通訊作者 | |
| 國別 | SGP |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 出處 | 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), pp.1453 - 1456 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70319 ) |