會議論文
| 學年 | 97 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2008-11-03 |
| 作品名稱 | A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage |
| 作品名稱（其他語言） | |
| 著者 | Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | IEEE Solid-State Circuits Society (IEEE SSCS) |
| 會議名稱 | 2008 IEEE Asian Solid-State Circuit Conference (A-SSCC '08) |
| 會議地點 | Fukuoka, Japan |
| 摘要 | This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130nm CMOS technology, the measured operation rate of 8bit x 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48mW from 0.5-V power supply. This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130 nm CMOS technology, the measured operation rate of 8bit times 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48 mW from 0.5-V power supply. |
| 關鍵字 | |
| 語言 | en_US |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20081103~20081105 |
| 通訊作者 | |
| 國別 | JPN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | 2008 IEEE Asian Solid-State Circuit Conference (A-SSCC '08), pp.73 - 76 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70215 ) |