會議論文

學年 104
學期 1
發表日期 2015-11-09
作品名稱 Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process
作品名稱(其他語言)
著者 Wei-Bin Yang; Yu-Yao Lin; Chi-Hsiung Wang; Kuo-Ning Chang; Cing-Huan Chen; Yu-Lung Lo
作品所屬單位
出版者
會議名稱 International Symposium on Intelligent Signal Processing and Communication Systems
會議地點 峇厘島, 印尼
摘要 In this paper, we analyze the circuit characteristic of static CMOS logics and provide the size ratio of PMOS to NMOS transistors under process, voltage and temperature (PVT) variations in UMC 0.18 μm CMOS process. The threshold voltage of a MOS transistor is influenced seriously under PVT variations with different channel length setting. The performances of the static CMOS logics are unstable in ultralow voltage. To find the best size ratio of PMOS to NMOS transistors, NOT gate are simulated with various channel length setting and PVT conditions. Five stages of NOT gate are designed by different ratios respectively to compose the ring oscillator. By examining oscillator output frequency, then we analyze the change of current according to various channel length and PVT conditions. By further analyzing the simulation results, if the channel length of MOS transistors is shorter than 300nm, or the supply voltage is lower than 0.9 V, then the performance of MOS transistors is unstable in UMC 0.18 μm CMOS process. Through the data and the simulation provided by this paper, we can design the circuits with different needs, and we can also understand how each different section of PVT variations and channel length setting will affect the circuit in UMC 0.18 μm CMOS process.
關鍵字 UMC 0.18um CMOS process;size ratio;ProcessVoltage-Temperature (PVT) variations;threshold voltage;ultralow voltage
語言 en
收錄於
會議性質 國際
校內研討會地點
研討會時間 20151109~20151112
通訊作者
國別 IDN
公開徵稿
出版型式
出處 ISPACS proceeding , pp.57-61
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/107356 )