會議論文
| 學年 | 94 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2005-08-29 |
| 作品名稱 | The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle |
| 作品名稱（其他語言） | |
| 著者 | Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | |
| 會議地點 | Ireland |
| 摘要 | Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V. |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20050829~20050902 |
| 通訊作者 | |
| 國別 | |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | 2005 European Conference on Circuit Theory and Design |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70582 ) |