會議論文
| 學年 | 92 |
|---|---|
| 學期 | 2 |
| 發表日期 | 2004-05-23 |
| 作品名稱 | A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop |
| 作品名稱（其他語言） | |
| 著者 | Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | IEEE; Circuits and Systems Society |
| 會議名稱 | The 2004 International Symposium on Circuits and Systems (ISCAS '04) |
| 會議地點 | Vancouver, Canada |
| 摘要 | A dual-slope frequency detector and charge pump architecture to achieve fast locking of phased-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A course-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.35 μm 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurements results show that the propose PLL has fast locking properties. |
| 關鍵字 | |
| 語言 | en_US |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20040523~20040526 |
| 通訊作者 | |
| 國別 | CAN |
| 公開徵稿 | Y |
| 出版型式 | 紙本 |
| 出處 | The 2004 International Symposium on Circuits and Systems (ISCAS '04), pp.892 - 896 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70233 ) |