511 |
95-2
|
參與學術服務
|
輔仁電子
|
512 |
92-2
|
學術演講
|
成功大學電機系 93年度S&IP 聯盟課程成果發表面 IP Testing
|
513 |
92-1
|
學術演講
|
輔仁大學電子工程學系 A Data-Path Based Diagnosis Mechanism for RTL Description of VLSI Circuits
|
514 |
88-2
|
會議論文
|
A timing-driven pseudo-exhaustive testing of VLSI circuits
|
515 |
94-2
|
會議論文
|
A broadcast-based test scheme for reducing test size and application time
|
516 |
93-2
|
會議論文
|
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
517 |
92-1
|
會議論文
|
The TAM Architecture for Optimal Testing Scheduling of SOC
|
518 |
90-1
|
會議論文
|
The methods to construct imaging circuit for efficient VLSI circuit verification
|
519 |
92-1
|
會議論文
|
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
|
520 |
92-1
|
會議論文
|
The Optimal Layout-Based Multi-Scan-Chain Scheme
|
521 |
92-1
|
會議論文
|
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
522 |
91-1
|
會議論文
|
An Efficient Test Strategy for Fast Multiplier Cores
|
523 |
90-1
|
會議論文
|
A TLS-Based Output Response Analyzer for BIST
|
524 |
91-1
|
會議論文
|
A Data-Path Based Diagnosis Mechanism for RTL Description of VLSI Circuits
|
525 |
90-1
|
會議論文
|
A Low Power All Digital If-Discriminator Design
|
526 |
92-1
|
研究報告
|
無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一提昇私校研發能量專案計畫-無線光傳收機之研製(I)
|
527 |
92-1
|
研究報告
|
以資料路徑為基礎之超大型積體電路暫存器轉移層次描述的驗證與診斷方法
|
528 |
93-1
|
研究報告
|
無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一:無線光傳收機之研製(II)
|
529 |
94-1
|
研究報告
|
無線光通訊之智慧型盲人預警監控及導引網路系統---子計畫一:提昇私校研發能量專案計畫---無線光傳收機之研製(III)
|
530 |
95-1
|
研究報告
|
超大積體電路之低功率及快速測試架構之探討
|
531 |
89-1
|
研究報告
|
超大型積體電路與系統設計---IP Testing
|
532 |
92-2
|
期刊論文
|
Built-In Reseeding With Modifying Technique For Bist
|
533 |
92-2
|
期刊論文
|
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
|
534 |
92-2
|
期刊論文
|
The optimal testrail architecture for core-based soc testing
|
535 |
97-1
|
期刊論文
|
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
|
536 |
96-2
|
期刊論文
|
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
537 |
99-1
|
期刊論文
|
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
|