| Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs | |
|---|---|
| 學年 | 99 |
| 學期 | 1 |
| 出版（發表）日期 | 2010-09-01 |
| 作品名稱 | Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | 臺北縣：淡江大學 |
| 著錄名稱、卷期、頁數 | 淡江理工學刊=Tamkang Journal of Science and Engineering 13(3)，頁305-314 |
| 摘要 | In this paper, we propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. The control signal combination causes the computing time increasing exponentially, and the algorithm we proposed introduces a heuristic control signal selecting method to solve this serious problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. The results show that it could significantly reduces both the test application time and the computation time. |
| 關鍵字 | |
| 語言 | en |
| ISSN | 1560-6686 |
| 期刊性質 | 國內 |
| 收錄於 | EI |
| 產學合作 | |
| 通訊作者 | Rau, Jiann-Chyi |
| 審稿制度 | 否 |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | ,紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/52816 ) |
| SDGS | 產業創新與基礎設施 |
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