| A broadcast-based test scheme for reducing test size and application time | |
|---|---|
| 學年 | 94 |
| 學期 | 2 |
| 發表日期 | 2006-05-21 |
| 作品名稱 | A broadcast-based test scheme for reducing test size and application time |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) |
| 會議名稱 | Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on |
| 會議地點 | Island of Kos, Greece |
| 摘要 | We present efficient method for reducing test application time by broadcasting test configuration. We compare our method based on single, multiple, 1-1 in-order mapping, even distribution, nearest signal probability matching, and in-order pseudo-exhaustive method. The results of our experiments indicate that our method reducing the test pattern number and the test application time by running the ATPG tool provided by SIS. |
| 關鍵字 | VLSI; Testing; BIST; Test Size; Test Application Time |
| 語言 | en |
| 收錄於 | |
| 會議性質 | |
| 校內研討會地點 | |
| 研討會時間 | 20060521~20060524 |
| 通訊作者 | |
| 國別 | GRC |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, pp.21-24 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/39040 ) |
| SDGS | 產業創新與基礎設施 |
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