A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
學年 96
學期 2
出版（發表）日期 2008-06-01
作品名稱 A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
作品名稱（其他語言）
著者 Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu
單位 淡江大學電機工程學系
出版者 臺北縣：淡江大學
著錄名稱、卷期、頁數 淡江理工學刊=Tamkang journal of science and engineering 11(2)，頁175-184
摘要 During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns can't detect fault (called useless patterns). In order to reduce the test time, we can remove useless patterns or change them to useful patterns (fault dropping). In fact, a random test set includes many useless patterns. Therefore we present a technology, including both reseeding and bit modifying (a.k.a. pattern mapping) to remove useless patterns or change them to useful patterns. When patterns changed, we pick out number of different fewer bits, leading to very short test length. Then we use an additional bit counter to improve test length and achieve high fault coverage. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with less test time.
關鍵字
語言 en
ISSN 1560-6686
期刊性質 國際
收錄於 EI
產學合作
通訊作者 Rau, Jiann-chyi
審稿制度 否
國別 TWN
公開徵稿
出版型式 紙本
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