教師資料查詢 | 類別: 會議論文 | 教師: 饒建奇 Jiann-chyi Rau (瀏覽個人網頁)

標題:A timing-driven pseudo-exhaustive testing of VLSI circuits
學年88
學期2
發表日期2000/05/28
作品名稱A timing-driven pseudo-exhaustive testing of VLSI circuits
作品名稱(其他語言)
著者Chang, S. C.; Rau, J. C.
作品所屬單位淡江大學電機工程學系
出版者Institute of Electrical and Electronics Engineers (IEEE)
會議名稱Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
會議地點Geneva, Switzerland
摘要The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.
關鍵字
語言英文
收錄於
會議性質國際
校內研討會地點
研討會時間20000528~20000531
通訊作者
國別瑞士
公開徵稿
出版型式紙本
出處Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on (Volume:2 ), pp.665-668
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