090 / 1 |
A Low Power All Digital If-Discriminator Design
|
#09.產業創新與基礎設施
|
2010-06-16 |
091 / 1 |
A Data-Path Based Diagnosis Mechanism for RTL Description of VLSI Circuits
|
#09.產業創新與基礎設施
|
2010-06-16 |
090 / 1 |
A TLS-Based Output Response Analyzer for BIST
|
#09.產業創新與基礎設施
|
2010-06-16 |
091 / 1 |
An Efficient Test Strategy for Fast Multiplier Cores
|
#09.產業創新與基礎設施
|
2010-06-16 |
092 / 1 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
#09.產業創新與基礎設施
|
2010-06-16 |
092 / 1 |
The Optimal Layout-Based Multi-Scan-Chain Scheme
|
#09.產業創新與基礎設施
|
2010-06-16 |
092 / 1 |
An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST
|
#09.產業創新與基礎設施
|
2010-06-16 |
090 / 1 |
The methods to construct imaging circuit for efficient VLSI circuit verification
|
#09.產業創新與基礎設施
|
2010-06-16 |
092 / 1 |
The TAM Architecture for Optimal Testing Scheduling of SOC
|
#09.產業創新與基礎設施
|
2010-06-16 |
093 / 2 |
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
|
#09.產業創新與基礎設施
|
2015-08-04 |
094 / 2 |
A broadcast-based test scheme for reducing test size and application time
|
#09.產業創新與基礎設施
|
2015-08-05 |
088 / 2 |
A timing-driven pseudo-exhaustive testing of VLSI circuits
|
#10.減少不平等
|
2015-07-27 |
097 / 1 |
The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design
|
#09.產業創新與基礎設施
|
2014-07-30 |
097 / 1 |
Test Slice Difference Technique for Low Power Testing
|
#09.產業創新與基礎設施
|
2011-10-23 |
096 / 2 |
An Efficient Test-Data Compaction for Low Power VLSI Testing
|
#09.產業創新與基礎設施
|
2011-10-23 |
096 / 1 |
A Novel High-Speed SOC Test Scheme Using Virtual TAMs
|
#09.產業創新與基礎設施
|
2011-10-23 |
097 / 2 |
A Novel Clock Gating Scheme of Scan Chains for Capture Power Reduction
|
#09.產業創新與基礎設施
|
2011-10-23 |
097 / 2 |
A Novel Constructive Data Compression Scheme for Shifting-in Power Reduction with Multiple Scan-chains Design
|
#09.產業創新與基礎設施
|
2011-10-23 |
098 / 2 |
Multi-Chains Encoding Scheme in Low-Cost ATE
|
#09.產業創新與基礎設施
|
2014-08-21 |
097 / 2 |
Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression
|
#09.產業創新與基礎設施
|
2014-09-23 |
099 / 1 |
An Filling Methodology for Efficient Compaction of Test Responses with Unknowns
|
#09.產業創新與基礎設施
|
2011-10-23 |
095 / 1 |
Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs
|
#09.產業創新與基礎設施
|
2014-10-15 |
098 / 2 |
Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment
|
#09.產業創新與基礎設施
|
2014-08-21 |
095 / 2 |
A New Algorithm for Latch-Up Check Based on Look-Up Table
|
#09.產業創新與基礎設施
|
2011-10-23 |
098 / 1 |
A New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
|
#09.產業創新與基礎設施
|
2015-03-10 |
096 / 2 |
A New Double-edge Triggered Design with Low-power consumption and High-speed
|
|
2011-10-23 |
092 / 1 |
A Datapath-Based Debugging Mechanism for RTL Description
|
#09.產業創新與基礎設施
|
2011-10-23 |
098 / 1 |
A Novel Gated Scan-Cell Scheme for Low Capture Power (LCP) in At-Speed Testing
|
#09.產業創新與基礎設施
|
2011-10-23 |
097 / 1 |
An Efficient Scheduling Algorithm for Testing SOC with Multi-Frequency TAM
|
|
2011-10-23 |
094 / 1 |
智慧型無線光導盲杖導引系統暨導盲機器人之設計
|
#09.產業創新與基礎設施
|
2014-06-05 |
100 / 1 |
Multiple Inputs Selector for High-Speed Masking
|
#09.產業創新與基礎設施
|
2013-07-25 |
101 / 1 |
Optimal Unknown Bit Filtering for Test Response Masking
|
#09.產業創新與基礎設施
|
2014-08-13 |
101 / 1 |
An Efficient Test Data Compression Scheme Using Selection Expansion
|
#09.產業創新與基礎設施
|
2013-07-25 |
101 / 1 |
Multimode ATPG for DVFS Designs
|
#09.產業創新與基礎設施
|
2013-07-25 |
092 / 1 |
A Datapath-Based Debugging Mechanism for RTL Description
|
#09.產業創新與基礎設施
|
2014-06-09 |
092 / 1 |
Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
|
#09.產業創新與基礎設施
|
2014-06-09 |
092 / 1 |
A Core-Based Test Methodology for Fast Multipliers
|
#09.產業創新與基礎設施
|
2014-06-09 |
091 / 1 |
A Novel BIST Response Analyzer Based on TLS
|
#09.產業創新與基礎設施
|
2014-06-06 |
093 / 1 |
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
|
#09.產業創新與基礎設施
|
2014-06-06 |
096 / 2 |
A New Low Power, High Speed Double-Edge Triggered Flip-Flop
|
#09.產業創新與基礎設施
|
2014-06-05 |
099 / 1 |
The AB-Filling Methodology for Power-aware At-Speed Scan Testing
|
#09.產業創新與基礎設施
|
2015-03-10 |
091 / 2 |
An efficient mechanism for debugging RTL description
|
#09.產業創新與基礎設施
|
2015-07-03 |
093 / 2 |
Reconfigurable multiple scan-chains for reducing test application time of SOCs
|
#09.產業創新與基礎設施
|
2015-08-04 |
104 / 1 |
重分佈層之避障繞線演算法
|
#09.產業創新與基礎設施
|
2016-04-01 |
105 / 1 |
應用無線分散式演算法於重分佈避障之研究
|
#09.產業創新與基礎設施
|
2017-02-24 |
105 / 1 |
使用環形振盪器對TSV預接合測試
|
#09.產業創新與基礎設施
|
2017-02-24 |
106 / 2 |
Low-Capture-Power X-filling Method Based On Architecture Using Selection Expansion
|
#09.產業創新與基礎設施
|
2019-05-13 |
108 / 1 |
一種基於測試模式特性的低功耗測試架構
|
#09.產業創新與基礎設施
|
2020-03-20 |
108 / 1 |
測試壓縮運用單輸入通道和多個擴展比
|
#09.產業創新與基礎設施
|
2020-03-20 |
110 / 1 |
A Scan-Based Lower-Power Testing Architecture for Modern Circuits
|
|
2022-03-07 |
110 / 1 |
基於EfficientNet之導引式雙層網路應用於超解析度影像
|
|
2022-03-07 |
111 / 2 |
基於 Mask R-CNN 的汽車圖像分割
|
|
2024-03-19 |
113 / 1 |
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism
|
|
2025-01-14 |