| 099 / 1 |
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
|
#09.產業創新與基礎設施
|
2017-03-08 |
| 096 / 2 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
#09.產業創新與基礎設施
|
2015-04-21 |
| 097 / 1 |
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
|
#09.產業創新與基礎設施
|
2013-10-01 |
| 092 / 2 |
The optimal testrail architecture for core-based soc testing
|
#09.產業創新與基礎設施
|
2010-06-16 |
| 092 / 2 |
An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information
|
#09.產業創新與基礎設施
|
2010-06-16 |
| 092 / 2 |
Built-In Reseeding With Modifying Technique For Bist
|
#09.產業創新與基礎設施
|
2016-12-27 |
| 089 / 1 |
Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
|
#09.產業創新與基礎設施
|
2013-12-20 |
| 089 / 1 |
A timing driven pseudo exhaustive testing for VLSI circuits
|
#09.產業創新與基礎設施
|
2016-12-16 |
| 092 / 2 |
以Layout為基礎的高效率多重掃描鍊最佳化
|
#09.產業創新與基礎設施
|
2012-05-03 |
| 096 / 2 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
#09.產業創新與基礎設施
|
2015-03-05 |
| 097 / 1 |
The Efficient TAM Design for Core-Based SOCs Testing
|
#09.產業創新與基礎設施
|
2013-09-05 |
| 099 / 2 |
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
|
#09.產業創新與基礎設施
|
2016-12-21 |
| 099 / 1 |
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
|
#09.產業創新與基礎設施
|
2015-01-22 |
| 099 / 2 |
Power-aware compression scheme for multiple scan-chain
|
#09.產業創新與基礎設施
|
2015-02-04 |
| 101 / 1 |
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
|
#09.產業創新與基礎設施
|
2024-03-25 |
| 100 / 2 |
Test Slice Difference Technique for Low-Transition Test Data Compression
|
#09.產業創新與基礎設施
|
2024-03-01 |
| 100 / 1 |
Multimode ATPG for DVFS Designs
|
#09.產業創新與基礎設施
|
2013-03-17 |