期刊論文
| 學年 | 89 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2000-10-01 |
| 作品名稱 | Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L. |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | The Institution of Engineering and Technology(IET) |
| 著錄名稱、卷期、頁數 | IEE Proceedings - Computers and Digital Techniques 147(5), pp.343-348 |
| 摘要 | A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaustive test patterns for both combinational and sequential VLSI circuit is presented. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme mainly contains three phases: backbone generation, tree growing, and XOR-tree generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging |
| 關鍵字 | |
| 語言 | en |
| ISSN | 1350-2387 1359-7027 |
| 期刊性質 | 國外 |
| 收錄於 | SCI EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | |
| 國別 | GBR |
| 公開徵稿 | |
| 出版型式 | 紙本 電子版 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60767 ) |