期刊論文
| 學年 | 97 |
|---|---|
| 學期 | 1 |
| 出版（發表）日期 | 2008-11-01 |
| 作品名稱 | The Efficient TAM Design for Core-Based SOCs Testing |
| 作品名稱（其他語言） | |
| 著者 | Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu |
| 單位 | 淡江大學電機工程學系 |
| 出版者 | Athens: World Scientific and Engineering Academy and Society (W S E A S) |
| 著錄名稱、卷期、頁數 | WSEAS Transactions on Circuits And Systems 11(7), pp.922-931 |
| 摘要 | This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC’02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms. Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test. |
| 關鍵字 | SOC Testing;TAM;Testing Scheduling |
| 語言 | en |
| ISSN | 1109-2734 |
| 期刊性質 | |
| 收錄於 | EI |
| 產學合作 | |
| 通訊作者 | |
| 審稿制度 | 國外 |
| 國別 | GRC |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/60953 ) |