會議論文
| 學年 | 96 |
|---|---|
| 學期 | 2 |
| 發表日期 | 2008-07-22 |
| 作品名稱 | A New Low Power, High Speed Double-Edge Triggered Flip-Flop |
| 作品名稱（其他語言） | |
| 著者 | Wu, Chung-Lin; Yang, Wei-Bin; Rau, Jiann-Chyi; Wang, Chi-Hsiung |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | |
| 會議名稱 | 2008亞太華人高速電路設計研討會(HSCD 2008) |
| 會議地點 | 臺北縣, 臺灣 |
| 摘要 | In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74% in compared with others. In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETFF) is proposed. A Double-edge triggered flip-flop is able to transfer the data signal in both positive edge and negative edge of the clock signal. Therefore, a lower clock rate can be used to such flip-flops and the power consumption can be reduced as compared with single edge-triggered flip-flops. By HSPICE simulation results, the power consumption is reduced by 0.2% to 55% and power-delay-product is reduced by 2% to 74 % in compared with others. |
| 關鍵字 | double-edge triggered;low power;high speed Best Regards Double-edge triggered;Low power;High speed Best Regard |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國內 |
| 校內研討會地點 | |
| 研討會時間 | 20080722~20080723 |
| 通訊作者 | |
| 國別 | TWN |
| 公開徵稿 | |
| 出版型式 | 紙本 |
| 出處 | 2008亞太華人高速電路設計研討會(HSCD 2008)論文集，5頁 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/70263 ) |