教師資料查詢 | 類別: 會議論文 | 教師: 鄭國興 CHENG KUO-HSING (瀏覽個人網頁)

標題:A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
學年
學期
發表日期1997/08/21
作品名稱A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
作品名稱(其他語言)
著者Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin
作品所屬單位淡江大學電機工程學系
出版者
會議名稱第八屆超大型積體電路設計暨計算機輔助設計技術研討會=The 8th VLSI Design/CAD Symposium
會議地點南投縣, 臺灣
摘要This paper describes circuit techniques for fabricating a 1.2V high-speed 32-bit adder using pass-transistor logic and without changing conventional 5V CMOS process. The low- power current-sensing complementary pass-transistor logic(LCSCPTL) is used in this design for its high operating speed and low power dissipation. A carry propagation circuit technique called conditional carry selection ( CCS) is used to resolve the problem of series-connected pass transistors in the carry propagation path. Based upon the HSPICE simulation, the operation speed of the LCSCPTL is about 2.2 times higher than the CPL. The power dissipation of the LCSCPTL is lower 40% than that of the CPL.
關鍵字加法器;互補式金氧半導體;架構;效能比較;方塊圖;Adder;Cmos;Architecture;Performance Comparison;Block Diagram
語言英文
收錄於
會議性質國內
校內研討會地點
研討會時間19970821~19970823
通訊作者
國別中華民國
公開徵稿Y
出版型式紙本
出處第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium頁349-352
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