Improving memory traffic by assembly-level exploitation of reuses for vector registers
學年 89
學期 1
出版（發表）日期 2000-09-01
作品名稱 Improving memory traffic by assembly-level exploitation of reuses for vector registers
作品名稱（其他語言）
著者 Chang, Chih-yung; Chen, T. S.; Sheu, J. P.
單位 淡江大學資訊工程學系
出版者
著錄名稱、卷期、頁數 The journal of supercomputing 17(2), pp.187-204
摘要 In this paper, we propose a compilation scheme to analyze and exploit the implicit reuses of vector register data. According to the reuse analysis, we present a translation strategy that translates the vectorized loops into assembly vector codes with exploitation of vector reuses. Experimental results show that our compilation technique can improve the execution time and traffic between shared memory and vector registers. Techniques discussed here are simple, systematic, and easy to be implemented in the conventional vector compilers or translators to enhance the data locality of vector registers.
關鍵字 data dependence;vector register;partial reuse;vector compilers;reuse distance;vectorization;supercomputer
語言 en
ISSN
期刊性質 國外
收錄於 SCI
產學合作
通訊作者
審稿制度 否
國別 TWN
公開徵稿
出版型式 ,電子版
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