專書單篇

學年 101
學期 1
出版(發表)日期 2012-08-01
作品名稱 Hardware accelerator design for image processing
作品名稱(其他語言)
著者 Li, Shih-An; Wong, Ching-Chang; Yang, Ching-Yang; Chen, Li-Feng
單位 淡江大學電機工程學系
出版者 Berlin, Heidelberg : Springer
著錄名稱、卷期、頁數 Advances in Autonomous Robotics: 
 Joint Proceedings of the 13th Annual TAROS Conference and the 15th Annual FIRA RoboWorld Congress, pp.436-437
摘要 This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
關鍵字 FPGA; human-machine interface; hardware accelerator
語言 en
ISBN 9783642325274
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