| 098 / 1 |
The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing
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2011-06-09 |
| 099 / 1 |
The Efficient TAM Design for Core-Based SOCs Testing
|
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2011-06-09 |
| 097 / 1 |
A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits
|
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2011-06-09 |
| 099 / 1 |
硬體描述語言VerilogHDL入門與應用
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2011-06-09 |
| 099 / 1 |
An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing
|
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2011-06-09 |
| 100 / 1 |
An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
|
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2012-10-23 |
| 100 / 1 |
Power-Aware Multi-Chains Encoding Scheme for System-on-a-chip in Low-Cost Environment
|
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2012-10-23 |
| 100 / 1 |
Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs
|
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2012-10-23 |
| 101 / 1 |
Power-aware compression scheme for multiple scan-chain
|
|
2013-05-15 |
| 102 / 1 |
Test Slice Difference Technique For Low-Transition Test Data Compression
|
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2014-07-16 |
| 103 / 1 |
Compact Test Pattern Selection for Small Delay Defect
|
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2015-03-13 |
| 104 / 1 |
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
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2016-09-03 |