086 / 1 |
A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process
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2010-06-16 |
087 / 1 |
A linear current controlled delay element for low power applications
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2010-06-16 |
087 / 2 |
A programmagle delay element for low power PLL applications
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2010-06-16 |
087 / 1 |
An efficient FIR filter design for VLSI implementation
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2010-06-16 |
086 / 1 |
Low-voltage-swing low-power CMOS buffer
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2010-06-16 |
090 / 1 |
Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization
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2014-07-30 |
087 / 1 |
The design and analysis of pass-transistor logic for low power applicaations
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2010-06-16 |
084 / 1 |
低功率電流偵測互補式帶通電晶體邏輯設計及其在低電壓快速乘法器之使用
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2010-06-16 |
086 / 1 |
1.2V low-power dynamic complementary-pass-transistor logic
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2010-06-16 |
086 / 1 |
A 1.2 V low-power TSPC complementary pass transistor logic
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2010-06-16 |
087 / 1 |
Low-power all digital down connverter for IS-95 forward link demodulation
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2010-06-16 |
090 / 1 |
A difference detector PFD for low jitter PLL
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2015-07-29 |
083 / 1 |
High-speed BiCHOS domino logic family for low-voltage operation
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2010-06-16 |
083 / 1 |
High-speed biCHOS tristate buffer and carry lookahead adder circuit for Low-voltage operation
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2010-06-16 |
088 / 1 |
A low-jitter and low-power phase-locked loop design
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2015-07-27 |
088 / 1 |
The suggestion for CFS CMOS buffer
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2015-07-27 |
087 / 1 |
High efficient 3-input XOR for low-voltage low-power high-speed applications
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2015-07-27 |
082 / 2 |
Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit
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2015-07-08 |
085 / 2 |
Design of current mode operational amplifier with differential-input and differential-output
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2015-07-08 |
078 / 1 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI
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2014-09-04 |
080 / 2 |
High-speed four-phase CMOS logic for complex high-speed VLSI
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2014-09-04 |
091 / 1 |
MOS Charge Pump for Sub-2.0V Operation
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2014-06-06 |
091 / 1 |
Low-Voltage GHz Dynamic Logic Circuit Design
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2014-06-06 |
084 / 1 |
Rule Extraction for Isolated Speech Recognition
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2014-02-13 |
086 / 1 |
A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
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2014-06-09 |
086 / 1 |
The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer
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2014-06-09 |
086 / 1 |
A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
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2014-06-09 |
092 / 1 |
A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
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2014-06-09 |
092 / 1 |
Design of Low-Power Content Addressable Memory Cell
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2014-06-09 |
088 / 1 |
A Low-Power CMOS Output Buffer
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2014-06-09 |
087 / 1 |
The Improvement of Conditional Sum Adder for Low Power Applications
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2015-07-02 |
084 / 2 |
A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications
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2015-07-08 |
085 / 2 |
A suggestion for low-power current-sensing complementary pass-transistor logic interconnection
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2015-07-08 |
083 / 2 |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications
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2015-07-15 |
084 / 2 |
True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI
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2015-07-21 |
088 / 2 |
The Design and implementation of DCT/IDCT Chip with Novel Architecture
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2015-07-27 |
088 / 1 |
The novel efficient design of XOR/XNOR function for adder applications
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2015-07-27 |
088 / 1 |
The non-full voltage swing TSPC (NSTSPC) logic design
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2015-07-28 |
089 / 2 |
A new logic synthesis and optimization procedure
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2015-07-28 |
089 / 2 |
A low-power high driving ability voltage control oscillator used in PLL
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2015-07-28 |
090 / 1 |
A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency
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2015-07-29 |
090 / 1 |
Accurate current mirror with high output impedance
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2015-07-29 |
090 / 1 |
A 1.2 V 500 MHz 32-bit carry-lookahead adder
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2015-07-29 |
090 / 1 |
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning
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2015-07-31 |