會議論文
| 學年 | 90 |
|---|---|
| 學期 | 1 |
| 發表日期 | 2002-01-07 |
| 作品名稱 | Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization |
| 作品名稱（其他語言） | |
| 著者 | Cheng, Kuo-hsing; Cheng, Shun-wen |
| 作品所屬單位 | 淡江大學電機工程學系 |
| 出版者 | N.Y.: IEEE (Institute of Electrical and Electronic Engineers) |
| 會議名稱 | Proc. Joint ASP-DAC and Int'l VLSI design, ASPDAC 2002 |
| 會議地點 | Bangalore, Kannada |
| 摘要 | Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the authors: "does any rule exist that contains all good?" This paper reveals novel logic synthesis and optimization procedures for full swing arbitrary logic function. The novel procedures are called prioritized prime implicant patterns puzzle (PPIPP). Following the proposed procedures, we can get a new hybrid high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and is suitable for low supply voltage. It has full swing signal in all nodes and high robustness against transistor downsizing and voltage scaling |
| 關鍵字 | |
| 語言 | en |
| 收錄於 | |
| 會議性質 | 國際 |
| 校內研討會地點 | |
| 研討會時間 | 20020107~20020107 |
| 通訊作者 | |
| 國別 | IND |
| 公開徵稿 | |
| 出版型式 | |
| 出處 | Proc. Joint ASP-DAC and Int'l VLSI design, ASPDAC 2002, Banglore, pp.155-159 |
| 相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/38837 ) |