A dual-loop CDR circuit with dual-mode capacitor multiplier-based loop filter and active inductor ring VCO
學年 113
學期 1
出版（發表）日期 2024-12-02
作品名稱 A dual-loop CDR circuit with dual-mode capacitor multiplier-based loop filter and active inductor ring VCO
作品名稱（其他語言）
著者 Wei-Bin Yang; Che-Chia Chuang; Hsiao-Yen Peng
單位
出版者
著錄名稱、卷期、頁數 IET Conference Proceedings 2024(22)
摘要 This paper proposes A half-rate dual-loop clock and data recovery (CDR) circuit with dual-mode capacitor multiplier-based active loop filter and active inductor ring voltage controlled oscillators (VCO). The proposed capacitor multiplier-based active filter allows for changing the operational mode of the CDR circuit to adjust the loop bandwidth, thereby enhancing stability and reducing required area. The improved active inductor ring VCO features a wide tuning range and low power consumption. The proposed CDR is implemented in the 90 nm CMOS technology. The simulation results show that the rms jitter and the peak-to-peak jitter of the recovered data is 5.3ps and 31.1ps at 2.7-Gb/s data rate. For the recovered clock, the rms jitter and peak-to-peak jitter are 5.1ps and 28ps at 1.35 GHz clock frequency. This work consumes 11.2mW with 1.2V power supply.
關鍵字
語言 en_US
ISSN
期刊性質 國內
收錄於
產學合作
通訊作者
審稿制度 否
國別 GBR
公開徵稿
出版型式 ,電子版
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機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/128288 )

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