An 80x Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS
學年 107
學期 1
申請日期 2018-08-01
得獎人員 施鴻源 SHIH, HORNG-YUAN
得獎論文名稱 An 80x Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS
得獎等級 0
所屬類別 0
出版者 IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no.8, pp. 1528-1533, Aug. 2015
研究獎勵類別 5
備註
發表日期 2015-01-01