A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
學年 106
學期 1
出版（發表）日期 2018-01-01
作品名稱 A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
作品名稱（其他語言）
著者 Yu-Lung Lo; Wei-Bin Yang; Han-Hsien Wang; Cing-Huan Chen; Zi-Ang Huang
單位
出版者
著錄名稱、卷期、頁數 Microsystem Technologies 24(1), p.137–146
摘要 This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm2.
關鍵字
語言 en_US
ISSN
期刊性質 國外
收錄於 SCI EI
產學合作
通訊作者 Wei-Bin Yang
審稿制度 是
國別 DEU
公開徵稿
出版型式 ,電子版
相關連結

機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/112391 )

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